The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Aug. 11, 2022
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Yizhong Zhang, Suzhou, CN;

Jie Jin, Suzhou, CN;

Stefano Pietri, Austin, TX (US);

Michael Todd Berens, Austin, TX (US);

Hongyan Yao, Suzhou, CN;

Jiawei Fu, Suzhou, CN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/66 (2006.01); H03M 1/68 (2006.01); H03M 1/76 (2006.01); H03M 1/78 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1057 (2013.01); H03M 1/66 (2013.01); H03M 1/687 (2013.01); H03M 1/765 (2013.01); H03M 1/785 (2013.01);
Abstract

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fbased on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fwith a high frequency clock having a constant frequency f. A memory is included to store at least two counter values generating by comparing fand fonce when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.


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