The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Aug. 17, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Arvin Cedric Quiambao Mallari, San Fernando, PH;

Maricel Fabia Escano, Angeles, PH;

Armando Tresvalles Clarina, Jr., La Trinidad, PH;

Jovenic Romero Esquejo, Baguio, PH;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 24/13 (2013.01); H01L 23/3107 (2013.01); H01L 23/49513 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/48 (2013.01); H01L 2224/022 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/11011 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/11903 (2013.01); H01L 2224/13006 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13164 (2013.01); H01L 2224/1357 (2013.01); H01L 2224/13582 (2013.01); H01L 2224/13611 (2013.01); H01L 2224/13639 (2013.01); H01L 2224/13644 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/13664 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/48247 (2013.01);
Abstract

In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.


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