The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2024
Filed:
Feb. 16, 2021
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Jungwoo Joh, Allen, TX (US);
Young-Joon Park, Plano, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 29/78 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/486 (2013.01); H01L 21/76802 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 29/7816 (2013.01); H05K 1/0216 (2013.01);
Abstract
A semiconductor device a strapped interconnect line, which in turn includes a first interconnect line at a first level above a semiconductor substrate, and a second interconnect line at a second level above the interconnect substrate. A dielectric capping layer is located directly on the first interconnect line. A plurality of strapping vias are connected between the first interconnect line and the second interconnect line. Each of the strapping vias extends from a first side of the first interconnect line to a second side of the second interconnect line.