The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Dec. 26, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Patrick G. Kutch, Tigard, OR (US);

Andrey Chilikin, Limerick, IE;

Niall D. McDonnell, Limerick, IE;

Brian A. Keating, Shannon, IE;

Naveen Lakkakula, Chandler, AZ (US);

Ilango S. Ganga, Cupertino, CA (US);

Venkidesh Krishna Iyer, Chandler, AZ (US);

Patrick Fleming, Slatt Wolfhill, IE;

Lokpraveen Mosur, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 3/06 (2006.01); G06F 9/50 (2006.01); G06F 12/0802 (2016.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 3/0604 (2013.01); G06F 3/061 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 9/5083 (2013.01); G06F 12/0802 (2013.01); G06F 13/4221 (2013.01); G06F 2212/6042 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/40 (2013.01);
Abstract

Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.


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