The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2024
Filed:
Jul. 20, 2023
Intel Corporation, Santa Clara, CA (US);
Hwa Chaw Law, Kuala Langat, MY;
Kiun Kiet Jong, George Town, MY;
Intel Corporation, Santa Clara, CA (US);
Abstract
An inter-die double data rate (DDR) data transfer scheme is provided. In particular, the data transfer scheme utilizes an error correction code (ECC) encoding scheme that exploits the DDR property that a single microbump defect can only yield four possible error scenarios. A specialized single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) encoding scheme that imposes at least four parity check matrix constraints may be used. Configured and operated in this way, a fewer number of parity check bits are required to detect data bit errors associated with a single defective microbump.