The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Jul. 08, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Justin Eno, El Dorado Hills, CA (US);

William A. Melton, Shingle Springs, CA (US);

Sean S. Eilert, Penryn, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/073 (2013.01); G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 11/1064 (2013.01); G06F 11/3037 (2013.01);
Abstract

Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.


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