The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Aug. 22, 2019
Applicant:

Everspin Technologies, Inc., Chandler, AZ (US);

Inventors:

Sanjeev Aggarwal, Scottsdale, AZ (US);

Sarin Deshpande, San Jose, CA (US);

Kerry Nagel, Scottsdale, AZ (US);

Santosh Karre, Chandler, AZ (US);

Assignee:

EVERSPIN TECHNOLOGIES, INC., Chandler, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 50/01 (2023.01); H10N 50/80 (2023.01); H01F 10/32 (2006.01); H10B 61/00 (2023.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); H10N 50/80 (2023.02); H01F 10/3254 (2013.01); H01F 10/3272 (2013.01); H10B 61/00 (2023.02);
Abstract

Fabrication of a magnetic memory element, including a via () in an interlevel dielectric layer (), providing an electrical connection between an underlying metal region () and a magnetoresistive stack device, such as a magnetic tunnel junction (), involves forming a transition metal layer () in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer () above, and/or a cap layer () below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.


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