The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Jul. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ajay Gupta, Portland, OR (US);

Ravikumar Balakrishnan, Beaverton, OR (US);

Shahrnaz Azizi, Cupertino, CA (US);

Maruti Gupta Hyde, Portland, OR (US);

Ariela Zeira, Encinitas, CA (US);

Arjun Anand, Santa Clara, CA (US);

Jacob Winick, Seattle, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 43/0852 (2022.01); G06F 1/3203 (2019.01); H04L 47/10 (2022.01); H04L 47/50 (2022.01);
U.S. Cl.
CPC ...
H04L 43/0852 (2013.01); G06F 1/3203 (2013.01); H04L 47/10 (2013.01); H04L 47/50 (2013.01);
Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed that generate dynamic latency values. An example apparatus includes an active status controller to determine that a modem is active based on a number of packets obtained from a network, a prediction controller to predict that the number of packets are indicative of a workload type based on a trained model, and a latency value generator to generate a latency value based on the workload type of the number of packets, the latency value to cause a processor processing the number of packets to enter a power saving state or a power executing state.


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