The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

May. 31, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Michael Mishaeli, Zichron Yaakov, IL;

Jason W. Brandt, Austin, TX (US);

Gilbert Neiger, Portland, OR (US);

Asit K. Mallick, Saratoga, CA (US);

Rajesh M. Sankaran, Portland, OR (US);

Raghunandan Makaram, Northborough, MA (US);

Benjamin C. Chaffin, Portland, OR (US);

James B. Crossland, Banks, OR (US);

H. Peter Anvin, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3009 (2013.01); G06F 9/3004 (2013.01); G06F 9/30076 (2013.01); G06F 9/3851 (2013.01); G06F 9/485 (2013.01); G06F 13/4068 (2013.01);
Abstract

A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.


Find Patent Forward Citations

Loading…