The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Dec. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Daniel Gruber, St. Andrae, AT;

Matteo Camponeschi, Villach, AT;

Christian Lindholm, Villach, AT;

Martin Clara, Santa Clara, CA (US);

Giacomo Cascio, Villach, AT;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03K 3/02 (2006.01); H04B 1/16 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0609 (2013.01); H03K 3/02 (2013.01); H04B 1/16 (2013.01);
Abstract

An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.


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