The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Apr. 18, 2022
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Che-Jui Hsu, Taichung, TW;

Ying-Fu Tung, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/28 (2006.01); H01L 21/3115 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/40114 (2019.08); H01L 29/42336 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A method of forming a semiconductor structure includes forming a mask layer on a substrate. The mask layer and the substrate include an opening. An isolation structure is formed in the opening. The mask layer is removed. A first conductive layer is formed on the isolation structure and the substrate. A first implantation process is performed on the first conductive layer and the isolation structure, to form a doped portion in the first conductive layer and a doped portion in the isolation structure. A second conductive layer is formed on the first conductive layer and the isolation structure. A first planarization process is performed, so that the top surfaces of the second conductive layer, the first conductive layer, and the isolation structure are aligned.


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