The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Mar. 22, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sungmoon Lee, Suwon-si, KR;

Minchan Gwak, Hwaseong-si, KR;

Heonjong Shin, Yongin-si, KR;

Yongsik Jeong, Suwon-si, KR;

Yeongchang Roh, Gwangju, KR;

Doohyun Lee, Hwaseong-si, KR;

Sunghun Jung, Suwon-si, KR;

Sangwon Jee, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/308 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/28114 (2013.01); H01L 21/28247 (2013.01); H01L 21/3083 (2013.01); H01L 21/32139 (2013.01); H01L 21/76883 (2013.01); H01L 21/76885 (2013.01); H01L 21/76892 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/5283 (2013.01); H01L 29/41783 (2013.01); H01L 29/41791 (2013.01); H01L 29/42376 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.


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