The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2024
Filed:
Mar. 14, 2020
Intel Corporation, Santa Clara, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Ben Ashbaugh, Folsom, CA (US);
Scott Janus, Loomis, CA (US);
Aravindh Anantaraman, Folsom, CA (US);
Abhishek R. Appu, El Dorado Hills, CA (US);
Niranjan Cooray, Folsom, CA (US);
Varghese George, Folsom, CA (US);
Arthur Hunter, Cameron Park, CA (US);
Brent E. Insko, Portland, OR (US);
Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
Selvakumar Panneer, Portland, OR (US);
Vasanth Ranganathan, El Dorado Hills, CA (US);
Joydeep Ray, Folsom, CA (US);
Kamal Sinha, Rancho Cordova, CA (US);
Lakshminarayanan Striramassarma, Folsom, CA (US);
Prasoonkumar Surti, Folsom, CA (US);
Saurabh Tangri, Folsom, CA (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.