The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Jul. 24, 2023
Applicants:

Tdk Corporation, Tokyo, JP;

Tdk Electronics Ag, Munich, DE;

Inventors:

Pirmin Hermann Otto Rombach, Kongens Lyngby, DK;

Kurt Rasmussen, Herlev, DK;

Dennis Mortensen, Bagsvard, DK;

Cheng-Yen Liu, Søborg, DK;

Morten Ginnerup, Kongens Lyngby, DK;

Jan Tue Ravnkilde, Hedehusene, DK;

Jotaro Akiyama, Tokyo, JP;

Assignees:

TDK Electronics AG, Munich, DE;

TDK Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 3/00 (2006.01); B81C 1/00 (2006.01); H04R 1/08 (2006.01);
U.S. Cl.
CPC ...
B81B 3/0051 (2013.01); B81C 1/00158 (2013.01); H04R 1/08 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0127 (2013.01); B81C 2201/053 (2013.01); B81C 2201/056 (2013.01); H04R 2201/003 (2013.01);
Abstract

In an embodiment, a method for fabricating a Microelectromechanical System (MEMS) microphone includes depositing, on a frontside of a wafer, a first oxide layer over a silicon nitride thin film and over and adjacent the wafer, wherein the silicon nitride thin film is disposed over the wafer, depositing a membrane protection layer over the first oxide layer between a first side of a first cavity formed in the wafer and a second side of a second cavity formed in the wafer, depositing a second oxide layer over and adjacent the membrane protection layer, depositing a first membrane nitride layer over the second oxide layer, depositing a membrane polysilicon layer over the first membrane nitride layer, depositing a second membrane nitride layer over the membrane polysilicon layer, depositing a third oxide layer over the second membrane nitride layer and depositing a fourth oxide layer over the third oxide layer.


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