The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Jul. 06, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Chao Lin, Hsinchu, TW;

Yu-Sheng Chen, Taoyuan, TW;

Carlos H. Diaz, Los Altos Hills, CA (US);

Da-Ching Chiou, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/20 (2023.01); H01L 23/528 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10N 70/231 (2023.02); H01L 23/5283 (2013.01); H10B 63/00 (2023.02); H10N 70/063 (2023.02); H10N 70/8265 (2023.02); H10N 70/841 (2023.02); H10N 70/8616 (2023.02);
Abstract

A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.


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