The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Jul. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Timothy Vasen, Linthicum Heights, MD (US);

Mark Van Dal, Linden, BE;

Gerben Doornbos, Kessel-Lo, BE;

Matthias Passlack, Hayward, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 10/46 (2023.01); H10K 19/10 (2023.01); H10K 85/20 (2023.01);
U.S. Cl.
CPC ...
H10K 10/484 (2023.02); H10K 10/464 (2023.02); H10K 10/472 (2023.02); H10K 10/481 (2023.02); H10K 19/10 (2023.02); H10K 85/221 (2023.02);
Abstract

In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.


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