The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

May. 27, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sushil Subramanian, Beaverton, OR (US);

Stefano Pellerano, Beaverton, OR (US);

Todor Mladenov, Portland, OR (US);

JongSeok Park, Hillsboro, OR (US);

Bishnu Prasad Patra, Zoetermeer, NL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/92 (2006.01); G06N 10/40 (2022.01); H03M 1/66 (2006.01); H10N 60/10 (2023.01);
U.S. Cl.
CPC ...
H03K 17/92 (2013.01); G06N 10/40 (2022.01); H03M 1/66 (2013.01); H10N 60/11 (2023.02); H10N 60/128 (2023.02);
Abstract

Technologies for the reduction of memory effects in a capacitor are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes an array of capacitors that can be charged to a voltage based on a voltage to be applied to a gate of the quantum processor. The capacitors in the array of capacitors are connected to the gate one at a time, charging up a parasitic capacitance. As more capacitors are switched, the voltage on the gate approaches a target voltage with an exponentially-decreasing voltage error.


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