The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

May. 03, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Wei Cheng Wu, Zhubei, TW;

Alexander Kalnitsky, San Francisco, CA (US);

Shih-Hao Lo, Zhubei, TW;

Hung-Pin Ko, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01);
Abstract

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a gate dielectric structure on a substrate. A sidewall spacer is formed around the gate dielectric structure. A metal structure is formed over the gate dielectric structure. A gate body layer is formed over the metal structure. A lower portion of the gate body layer is cupped by the metal structure. A top surface of the gate body layer is vertically offset from a top surface of the metal structure. A conductive via is formed over the metal structure. The conductive via is disposed between outer sidewalls of the gate body layer.


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