The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2024
Filed:
Dec. 23, 2021
Applicant:
Shinko Electric Industries Co., Ltd., Nagano, JP;
Inventor:
Satoshi Shiraki, Nagano, JP;
Assignee:
SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/053 (2006.01); H01L 23/495 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 23/49513 (2013.01); H01L 23/49558 (2013.01); H01L 23/49575 (2013.01); H01L 23/49582 (2013.01); H01L 23/49586 (2013.01); H01L 23/5329 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 23/053 (2013.01); H01L 23/49503 (2013.01);
Abstract
A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.