The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Mar. 11, 2021
Applicant:

Meiko Electronics Co., Ltd., Ayase, JP;

Inventor:

Shuzo Akejima, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/3677 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01); H01L 2225/1094 (2013.01);
Abstract

A memory device includes: a wiring substrate including a multilevel wiring layer and first and second surfaces at opposite sides; a control element embedded in the wiring substrate and having first and second element surfaces at opposite sides, with multiple electrode pads connected to the multilevel wiring layer at the first element surface; a first heat dissipation member at a region of the first surface overlapping the control element; a heat dissipation structure facing the second element surface and exposed at the second surface; and at least one memory element connected with the multilevel wiring layer at a first surface region not overlapping the control element. The multilevel wiring layer includes a signal pattern electrically connecting the control element with the memory element or the external connection terminal, and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member.


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