The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Mar. 16, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Tushar Praful Merchant, Austin, TX (US);

Mark Douglas Hall, Austin, TX (US);

Anirban Roy, Austin, TX (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/3065 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82385 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/28518 (2013.01); H01L 21/3065 (2013.01); H01L 21/823807 (2013.01); H01L 21/823864 (2013.01); H01L 27/0922 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (--) which are separated from one another by a barrier oxide layer () and which are separately processed to form first remnant silicon germanium nanosheet layers () in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG) and to form second remnant silicon germanium nanosheet layers () in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.


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