The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Apr. 05, 2021
Applicant:

Alexander Yuri Usenko, Belton, MO (US);

Inventor:

Alexander Yuri Usenko, Belton, MO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76256 (2013.01);
Abstract

A process for making silicon on insulator wafer by bond and etch back—BESOI. A boron etch stop is formed by BF2+ ion implantation followed by solid phase epitaxy—SPE. Fluorine getters metals for OISF immunity of the final wafer. SPE activates boron above solubility limit thus facilitates high etch selectivity. Future cap silicon film is epitaxially grown over the boron etch stop at temperature that limits boron diffusion and boron deactivation. High temperature hydrogen bake step in epitaxy is replaced with Siconi of similar low temperature process. Buried oxide is thermally grown from portion of cap silicon layer at temperature limiting Boron diffusion and deactivation. Thus, SOI wafer design is the same as in layer transfer process—bonding interface is at the bottom interface of BOX; properties of final SOI wafer are equal to SOI made by layer transfer process—including cap silicon layer thickness variation, and OISF defect count. Advantage over the layer transfer—this process does not require non-standard equipment. Standard processing tool set readily available at semiconductor foundries is sufficient to run this process. Foundries can use this process for in house SOI wafer manufacturing.


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