The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Aug. 11, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Nicola Colella, Capodrise, IT;

Antonino Pollio, Vico Equense, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0846 (2016.01); G06F 12/02 (2006.01); G06F 12/0804 (2016.01); G06F 12/0891 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0848 (2013.01); G06F 12/0246 (2013.01); G06F 12/0804 (2013.01); G06F 12/0891 (2013.01); G06F 2212/7201 (2013.01);
Abstract

Methods, systems, and devices for a split cache for address mapping data are described. A memory system may include a cache (e.g., including a first and second portion) for storing data that indicates a mapping between logical addresses associated with a host system and physical addresses of the memory system. The memory system may store data (e.g., the address mapping data) within the first portion of the cache. Additionally, the memory system may store an indication of whether the data is used for any access operations during a duration that the data is stored in the first portion of the cache. The memory system may transfer subsets of the data to the second portion of the cache if they are used for access operations during the duration.


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