The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2024
Filed:
Dec. 19, 2020
Intel Corporation, Santa Clara, CA (US);
Charles Augustine, Portland, OR (US);
Pascal Meinerzhagen, Hillsboro, OR (US);
Suyoung Bang, Hillsboro, OR (US);
Abdullah Afzal, Austin, TX (US);
Karthik Subramanian, Austin, TX (US);
Muhammad Khellah, Tigard, OR (US);
Arvind Raman, Austin, TX (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).