The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2024
Filed:
Jun. 26, 2023
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Ian Shaeffer, Los Gatos, CA (US);
Kyung Suk Oh, Cupertino, CA (US);
Assignee:
RAMBUS INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 7/22 (2006.01); G11C 11/4063 (2006.01); G11C 29/02 (2006.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 7/18 (2006.01); G11C 11/4097 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G11C 5/063 (2013.01); G11C 11/4063 (2013.01); G11C 29/02 (2013.01); G11C 29/022 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 7/18 (2013.01); G11C 11/4097 (2013.01);
Abstract
A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.