The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

Dec. 11, 2020
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Itai Avron, Petach Tikva, IL;

Erez Sabbag, Koranit, IL;

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); G11C 29/36 (2006.01); G11C 29/42 (2006.01); H03M 13/15 (2006.01); G06F 11/10 (2006.01); G11C 13/00 (2006.01); G11C 29/02 (2006.01); G11C 29/44 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1105 (2013.01); G11C 29/36 (2013.01); G11C 29/42 (2013.01); H03M 13/1515 (2013.01); H03M 13/152 (2013.01); G06F 11/1048 (2013.01); G11C 2013/0057 (2013.01); G11C 29/024 (2013.01); G11C 2029/3602 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01);
Abstract

A decoder is disclosed with error correction for memory data. The decoder's error correction is extended to additional faulty bits by integrating a memory test into the error correction to identify faulty bits in the memory data. A method for correction can include writing a known pattern to the failing address (and possibly to neighboring addresses), reading the known pattern back and comparing the read data to the written pattern to identify the failing bits. The failing bits are then used together with the error correction data to correct memory data having multiple incorrect bits or to alert other components about the failing bit locations.


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