The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2024
Filed:
Mar. 09, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventor:
Amit Kumar Srivastava, Folsom, CA (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/22 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); G06F 1/14 (2006.01); H03L 7/087 (2006.01); H03L 7/18 (2006.01); H03L 7/23 (2006.01); H03L 7/197 (2006.01); H03M 1/12 (2006.01); H03M 1/50 (2006.01);
U.S. Cl.
CPC ...
H03L 7/087 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); G06F 1/14 (2013.01); H03L 7/23 (2013.01); H03L 7/235 (2013.01); H03L 7/1976 (2013.01); H03M 1/1255 (2013.01); H03M 1/50 (2013.01);
Abstract
Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.