The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

Apr. 06, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Amitava Majumdar, Boise, ID (US);

Radhakrishna Kotti, Boise, ID (US);

Mallesh Rajashekharaiah, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01J 37/28 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10B 63/00 (2023.01); G11C 13/00 (2006.01); H01J 37/04 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01J 37/28 (2013.01); H01L 21/76802 (2013.01); H01L 21/76834 (2013.01); H01L 21/76877 (2013.01); H01L 23/5283 (2013.01); H10B 63/84 (2023.02); G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2213/71 (2013.01); H01J 37/04 (2013.01); H01J 2237/2804 (2013.01); H01J 2237/2814 (2013.01); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/8825 (2023.02);
Abstract

Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.


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