The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2024
Filed:
Jun. 30, 2021
Sambanova Systems, Inc., Palo Alto, CA (US);
Tejas Nagendra Babu Nama, Sunnyvale, CA (US);
Ruddhi Chaphekar, Santa Clara, CA (US);
Ram Sivaramakrishnan, San Jose, CA (US);
Raghu Prabhakar, San Jose, CA (US);
Sumti Jairath, Santa Clara, CA (US);
Junjue Wang, San Mateo, CA (US);
Kaizhao Liang, Palo Alto, CA (US);
Adi Fuchs, West Windsor, NJ (US);
Matheen Musaddiq, Austin, TX (US);
Arvind Krishna Sujeeth, San Francisco, CA (US);
SambaNova Systems, Inc., Palo Alto, CA (US);
Abstract
Disclosed is a data processing system that includes compile time logic to section a graph into a sequence of sections including a first section and a second section. The compile time logic is to configure the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section, and configure the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section. The data processing system further includes runtime logic configured with the compile time logic to execute the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations, and execute the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations.