Memory device and program operation thereof

Abstract

In certain aspects, a memory device includes an array of memory cells columns and rows, word lines respectively coupled to rows of the memory cells, bit lines respectively coupled to the columns of the memory cells, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row of the rows of the memory cells based on a current data page. Each memory cell is set to one of 2levels corresponding a piece of N-bits data, where N is an integer greater than 2. The peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit, N−1 data storage units, and a multipurpose storage unit. The cache storage unit is configured to sequentially receive N bits of the current data page and N bits of a next data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page. The data storage units each is configured to sequentially store a respective one of the N bits of the current data page and a respective one of the N bits of the next data page. The multipurpose storage unit is configured to store at least one of the N bits of the current data page.