The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2024
Filed:
Mar. 14, 2020
Intel Corporation, Santa Clara, CA (US);
Lakshminarayanan Striramassarma, Folsom, CA (US);
Prasoonkumar Surti, Folsom, CA (US);
Varghese George, Folsom, CA (US);
Ben Ashbaugh, Folsom, CA (US);
Aravindh Anantaraman, Folsom, CA (US);
Valentin Andrei, San Jose, CA (US);
Abhishek Appu, El Dorado Hills, CA (US);
Nicolas Galoppo Von Borries, Portland, OR (US);
Altug Koker, El Dorado Hills, CA (US);
Mike Macpherson, Portland, OR (US);
Subramaniam Maiyuran, Gold River, CA (US);
Nilay Mistry, Bangalore, IN;
Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
Selvakumar Panneer, Portland, OR (US);
Vasanth Ranganathan, El Dorado Hills, CA (US);
Joydeep Ray, Folsom, CA (US);
Ankur Shah, Folsom, CA (US);
Saurabh Tangri, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.