The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Jun. 16, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Raul Enriquez Shibayama, Zapopan, MX;

Carlos Alberto Lizalde Moreno, Guadalajara, MX;

Gaudencio Hernandez Sosa, Guadalajara, MX;

Kai Xiao, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 13/00 (2006.01); H01R 12/71 (2011.01); H01R 13/6469 (2011.01); H01R 13/6471 (2011.01); H05K 7/14 (2006.01);
U.S. Cl.
CPC ...
H01R 13/6469 (2013.01); H01R 12/718 (2013.01); H01R 13/6471 (2013.01); H05K 7/1452 (2013.01);
Abstract

Microelectronic assemblies, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a microelectronic device having a hexagonal node configuration, wherein the hexagonal node configuration may include a differential signal node pair; a power node; and a plurality of ground nodes; and wherein the differential signal node pair, the power node, and the plurality of ground nodes are arranged in a hexagonal parallelogon pattern, wherein the differential signal node pair includes a first differential signal node adjacent to a second differential signal node, and wherein the power node is adjacent and symmetric to the differential signal node pair; and a microelectronic substrate electrically coupled to the microelectronic device.


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