Semiconductor structures with via openings and methods of making the same

Abstract

The present disclosure discloses a semiconductor structure having an insulating layer disposed on a wafer active surface of a semiconductor wafer for covering the wafer active surface. The insulating layer may be a protective layer in some embodiments and a cover layer in other embodiments. The insulating layer has via openings to expose contact pads for leading out electrical connections. In particular, the via openings are formed by a multi-step etching process (such as a two-step etching process) without damaging the contact pads. The two-step etching process includes a first laser etching process using normal pulse (P) and normal energy to form partial via openings in the cover layer. The second etching process includes either a laser etching process using low P and low E or a plasma etching process. The second etching process avoids damaging the contact pads.