The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Jun. 17, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Win-San Khwa, Taipei, TW;

Yi-Lun Lu, New Taipei, TW;

Jui-Jen Wu, Hsinchu, TW;

Meng-Fan Chang, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/28 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 19/28 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01);
Abstract

The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.


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