The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

May. 06, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mariano Tepper, Santa Clara, CA (US);

Dipanjan Sengupta, Hillsboro, OR (US);

Sourabh Dongaonkar, Santa Clara, CA (US);

Chetan Chauhan, Folsom, CA (US);

Jawad Khan, Portland, OR (US);

Theodore Willke, Portland, OR (US);

Richard Coulson, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 16/23 (2019.01); G06F 7/58 (2006.01); G06F 9/30 (2018.01); G06F 16/13 (2019.01); G06F 16/22 (2019.01); G06F 16/2455 (2019.01); G06F 16/9535 (2019.01); G06F 16/9538 (2019.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 7/58 (2013.01); G06F 9/30036 (2013.01); G06F 16/137 (2019.01); G06F 16/2255 (2019.01); H01L 27/0688 (2013.01);
Abstract

Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.


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