The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Feb. 10, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Farah E. Fargo, Hudson, MA (US);

Mitchell Diamond, Shrewsbury, MA (US);

David Keppel, Mountain View, CA (US);

Samantika S. Sury, Westford, MA (US);

Binh Pham, Burlingame, CA (US);

Shobha Vissapragada, Hudson, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 2212/657 (2013.01);
Abstract

Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.


Find Patent Forward Citations

Loading…