Inline buffer for in-memory post package repair (ppr)

Abstract

In a memory system, a memory device has a memory array with multiple rows of memory having logical addresses mapped to their physical addresses and at least one spare row not having a logical address mapped to its physical address. A controller detects a failure of one of the multiple rows of memory ('failure row') and executes a post package repair (PPR) mode. The controller can be internal to the memory device or external to the memory device. The memory device includes an internal scratchpad to allow transfer of data contents from the failure row to the spare row. The controller can map the logical address of the failure row from the physical address of the failure row to the physical address of the spare row, transfer data contents from the failure row to the internal scratchpad, and transfer the data contents from the internal scratchpad to the spare row.