The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Mar. 14, 2019
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Sivananda Krishnan Kanakasabapathy, Pleasanton, CA (US);

Hui-Jung Wu, Pleasanton, CA (US);

Richard Wise, Los Gatos, CA (US);

Arpan Mahorowala, West Linn, OR (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 16/04 (2006.01); C23C 16/40 (2006.01); C23C 16/455 (2006.01); H01L 21/311 (2006.01); H01L 21/67 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
C23C 16/045 (2013.01); C23C 16/407 (2013.01); C23C 16/45553 (2013.01); H01L 21/31122 (2013.01); H01L 21/31144 (2013.01); H01L 21/67023 (2013.01); H01L 21/67069 (2013.01); H01L 21/76808 (2013.01);
Abstract

Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.


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