The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Jan. 11, 2021
Applicant:

Shanghai Hestia Power Inc., Shanghai, CN;

Inventors:

Chien-Chung Hung, Hsinchu, TW;

Kuo-Ting Chu, Hsinchu, TW;

Lurng-Shehng Lee, Hsinchu, TW;

Chwan-Yin Li, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/04 (2006.01); H01L 21/765 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/046 (2013.01); H01L 21/765 (2013.01); H01L 29/063 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/407 (2013.01); H01L 29/66068 (2013.01);
Abstract

A trench silicon carbide metal-oxide semiconductor field effect transistor includes a silicon carbide semiconductor substrate and a trench metal-oxide semiconductor field effect transistor, the field effect transistor includes a trench vertically arranged and penetrating along a first horizontal direction, a gate insulating layer formed on an inner wall of the trench, a first poly gate formed on the gate insulating layer, a shield region formed outsides and below the trench, and a field plate arranged between a bottom wall of the trench and the shield region, and the field plate has semiconductor doping and is laterally in contact to a current spreading layer to deplete electrons of the current spreading layer when a reverse bias voltage is applied.


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