The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Mar. 03, 2022
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Toru Sugiyama, Musashino, JP;

Akira Yoshioka, Yokohama, JP;

Yasuhiro Isobe, Ota, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/07 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/4952 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 25/0657 (2013.01); H01L 25/074 (2013.01); H01L 29/66431 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A first chip includes a first surface, a second surface, a first semiconductor layer including a nitride semiconductor layer, a first electrode pad located at the first surface, a second electrode pad located at the first surface, a first gate pad located at the first surface, and a third electrode pad located at the first surface. A second chip is located on the first surface of the first chip. The second chip includes a third surface facing the first surface of the first chip, a fourth surface, a second semiconductor layer including a channel of a second conductivity type, a fourth electrode pad located at the fourth surface, a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.


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