The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2024
Filed:
Jun. 06, 2023
Applicant:
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Inventors:
Shunpei Yamazaki, Tokyo, JP;
Kiyoshi Kato, Kanagawa, JP;
Takahiko Ishizu, Kanagawa, JP;
Tatsuya Onuki, Kanagawa, JP;
Assignee:
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G11C 11/408 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H10B 99/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4085 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/24 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); H10B 99/00 (2023.02);
Abstract
A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.