The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Dec. 21, 2022
Applicant:

Ceremorphic, Inc., San Jose, CA (US);

Inventors:

Venkat Mattela, San Jose, CA (US);

Heonchul Park, Pleasanton, CA (US);

Radhika Ponnamaneni, Telangana, IN;

Govardhan Mattela, Hyderabad, IN;

Assignee:

Ceremorphic, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3802 (2013.01); G06F 9/30101 (2013.01); G06F 9/382 (2013.01); G06F 9/3851 (2013.01); G06F 9/3873 (2013.01);
Abstract

A multi-stage processor has a pre-fetch stage, and a sequence of pipelined processor stages. A thread map register contains thread identifiers, and a thread map valid register has locations corresponding to the thread map register and indicating whether a value in the thread map register is to be fetched or not, and a thread map length register indicates the number of thread map register locations forming a canonical sequence of thread identifiers to the pre-fetch stage. The pre-fetch stage does not act on a thread identifier with a not valid thread map valid value, thereby saving power in low demand conditions.


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