The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Mar. 27, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sumeet Singh Nagi, Los Angeles, CA (US);

Farhana Sheikh, Portland, OR (US);

Scott Jeremy Weber, Piedmont, CA (US);

Uneeb Yaqub Rathore, Los Angeles, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/48 (2006.01); G06F 7/49 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 9/50 (2006.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 7/4806 (2013.01); G06F 7/49 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 9/5027 (2013.01); G06F 17/16 (2013.01);
Abstract

Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions using one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.


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