The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Aug. 10, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jung-Chan Yang, Hsinchu, TW;

Ting-Wei Chiang, Hsinchu, TW;

Jerry Chang-Jui Kao, Hsinchu, TW;

Hui-Zhong Zhuang, Hsinchu, TW;

Lee-Chung Lu, Hsinchu, TW;

Li-Chun Tien, Hsinchu, TW;

Meng-Hung Shen, Hsinchu, TW;

Shang-Chih Hsieh, Hsinchu, TW;

Chi-Yu Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H01L 2027/11887 (2013.01);
Abstract

A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.


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