The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Dec. 23, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Parijat Biswas, Benniganahalli, IN;

Badri Gopalan, Cupertino, CA (US);

Enzhi Ni, Shanghai, CN;

Danish Jawed, Indirapuram, IN;

Ying Chen, Shanghai, CN;

Jiang Chen, Shanghai, CN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G01R 31/3183 (2006.01); G06F 30/323 (2020.01); G06F 30/3308 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3308 (2020.01); G01R 31/31835 (2013.01); G01R 31/318357 (2013.01); G06F 30/323 (2020.01);
Abstract

A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL) is provided. The method includes identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables. The method can further include storing the identified connections in a database, and using, by a processor, connections retrieved from the database to simulate and verify the coverage areas of the IC design.


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