Erasable programmable single-ploy non-volatile memory cell and associated array structure

Abstract

An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.