The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Jun. 09, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Geunwon Lim, Yongin-si, KR;

Minjun Kang, Hwaseong-si, KR;

Byunggon Park, Seoul, KR;

Joongshik Shin, Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); G11C 7/18 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 41/40 (2023.02); G11C 7/18 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers.


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