The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Jun. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chi-Yi Chuang, Hsinchu, TW;

Ching-Wei Tsai, Hsinchu, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Chih-Hao Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/785 (2013.01);
Abstract

The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.


Find Patent Forward Citations

Loading…