The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Mar. 30, 2022
Applicant:

Huawei Technologies Co., Ltd., Guangdong, CN;

Inventors:

Zhaozheng Hou, Dongguan, CN;

Yunbin Gao, Shenzhen, CN;

Yiyu Wang, Dongguan, CN;

Fei Hu, Dongguan, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 29/16 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0619 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 23/49861 (2013.01); H01L 29/0607 (2013.01); H01L 29/1608 (2013.01); H01L 29/872 (2013.01);
Abstract

This application provides a power semiconductor device, which includes: a semiconductor substrate, where the semiconductor substrate is doped with a first-type impurity; an epitaxial layer, that is doped with the first-type impurity, the epitaxial layer is disposed on a surface of the semiconductor substrate, a first doped region doped with a second-type impurity is disposed on a first surface that is of the epitaxial layer and that is away from the semiconductor substrate, and a circumferential edge of the first surface of the epitaxial layer has a scribing region; a first metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate, where the first metal layer is electrically connected to the epitaxial layer; a second metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate; and a passivation layer.


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