The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2024
Filed:
Dec. 22, 2022
Applicant:
Adeia Semiconductor Technologies Llc, San Jose, CA (US);
Inventor:
Stephen Morein, San Jose, CA (US);
Assignee:
ADEIA SEMICONDUCTOR TECHNOLOGIES LLC, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/02 (2006.01); H01L 21/321 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 29/08 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H10B 99/00 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/02532 (2013.01); H01L 21/3212 (2013.01); H01L 21/76802 (2013.01); H01L 21/7684 (2013.01); H01L 21/76877 (2013.01); H01L 21/823418 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 21/823487 (2013.01); H01L 23/528 (2013.01); H01L 25/50 (2013.01); H01L 29/0847 (2013.01); H01L 29/45 (2013.01); H01L 29/665 (2013.01); H10B 99/00 (2023.02); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01);
Abstract
Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.